1. Field
Embodiments described herein relate to a nonvolatile semiconductor storage device.
2. Description of the Related Art
Memory cell transistors used in NAND flash memories have been increased in miniaturization with the advancement of their generation. However, the thinning of the insulating film has not kept up with the shortening of the transistor gate length. This causes a problem when data is written/erased or read using miniaturized memory cell transistors.
More specifically, there occurs a contradictory relationship between the short-channel effect which appears at the time of reading from a memory cell transistor and erroneous writing to an unselected memory cell at the time of writing to a NAND column. The short-channel effect is a phenomenon that when the gate length of a MIS transistor is made too short, the gate electrode cannot control the channel region and the transistor does not exhibit a clear on-off characteristic. To suppress the short-channel effect, it is necessary to increase the substrate impurity concentration of a transistor. However, when the substrate impurity concentration is increased, it becomes more difficult to increase the channel potential of unselected memory cells at the time of writing. If the channel potential of unselected memory cells is not increased sufficiently, a strong electric field is exerted on the insulating films of the unselected memory cells and hence erroneous writing is prone to occur.
On the other hand, when the substrate impurity concentration of a transistor is decreased, a remarkable short-channel effect appears at the time of reading though the probability of occurrence of erroneous writing becomes low. As described above, there is the contradictory relationship that the short-channel effect and the erroneous writing cannot be suppressed at the same time. This becomes more serious as the gate length is made shorter.
There is another problem which particularly relates to MONOS memory cells which employ an insulating film (silicon nitride film) as a charge storage layer. That is, when writing/erasure is performed repeatedly in a MONOS memory, defects are produced at a substrate interface (charge injection side), as a result of which the Id-Vg characteristic (transfer characteristic) of the memory cell transistors is degraded. In general, the charge storage layer is a conductive layer such as a floating gate electrode, discrete conductive layers of, for example, a nano-dot memory, an insulating layer having traps such as a silicon nitride film of MONOS (metal-oxide-nitride-oxide-silicon), or the like.
A technique for avoiding the above degradation is known in which p-channel MONOS transistors are formed. Wiring/erasure is performed by injecting carriers from the gate electrode side, and data is read out by channels formed on the opposite side, that is, at the substrate-side interface.
In US2007/0029625A, charge injection and data reading are performed by different regions. The gate electrode for charge injection is made of polycrystalline silicon having a high dopant impurity concentration or a metal. That is, a transistor having a channel region is not formed on the gate side. Therefore, whereas an inversion layer is formed on the gate side at the time of data reading by a charge supply control by a selection gate transistor, a depletion layer is formed (no inversion layer is formed) on the gate side in unselected cells at the time of writing. As exemplified by this, it is impossible to perform a control relating to the gate-side depletion layer. As such, US2007/0029625A has a disadvantage that the depletion layer existing only on the substrate side should play two roles, that is, expansion of the depletion layer in an unselected cell at the time of writing and suppression of the short-channel effect through reduction of the depletion layer width at the time of reading. This contradiction becomes more remarkable as memory cells are increased in miniaturization.